(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to providing an opening that facilitates Flex Enhanced BGA (FEBGA) and Enhanced BGA (EBGA) device verification thus improving ease of device handling and reducing errors that are introduced by incorrect handling of FEBGA/EBGA devices.
(2) Description of the Prior Art
The creation of semiconductor devices does not only require the application of complex technologies with complex processing conditions and sequences but further requires methods of packaging the semiconductor devices once the devices have been created. Due to increased device density and increased device complexity, input/output capabilities of semiconductor devices may become a device performance constraint and therefore place increased requirements on the packaging of semiconductor devices. Semiconductor device packages are known under a number of names and abbreviations and include laminated Ball Grid Array (BGA) devices that have over time evolved from lead frame packages such as the Dual In Line (DIL) and Quad Flat Package (QFP). BGA packages have shown to provide significant advantages that become especially important when the BGA approach is used to package an integrated circuit or die that has a high input/output pin count or where the semiconductor die is used in high-frequency applications. BGA packages can in addition be mounted using conventional surface mount and assembly techniques when these packages are mounted on a conventional Printed Circuit Board (PCB). The mounting of a semiconductor device typically requires the device, a substrate on which the device is to be mounted (such as a Printed Circuit Board), a method of connecting the die to the underlying substrate, which is typically referred to as first level interconnect and for which methods of wire bonding or Tape Automated Bond (TAB) or Controlled Collapse Chip Connection (C4) can be used, a method of connecting the substrate of the device to printed circuit cards or boards, also referred to as second level of interconnect that uses external metal pins or solder balls. Substrates typically contain ceramic or plastic materials, while semiconductor die can be encapsulated for reasons of protection whereby this encapsulation also encloses the first level of interconnect.
Surface mounted, high pin count integrated circuit packages have in the past been configured using Quad Flat Packs (QFP""s) with various pin configurations. These packages have closely spaced leads for making electrical connections distributed along the four edges of the flat package. These packages have become limited by being confined to the edges of the flat package even though the pin to pin spacing is small. To address this limitation, a new package, the Ball Grid Array (BGA) package, is increasingly used. This package is less confined in its I/O pin distribution because the electrical I/O contact points are distributed over the entire bottom surface of the package. More contact points can thus be located on the bottom of the package, with spacing between the contact points that is larger than the spacing that is typically found in QFP""s. These contacts are solder balls that facilitate flow soldering of the package onto a printed circuit board.
A Ball Grid Array (BGA) is an array of solderable balls placed on a chip carrier. The balls contact a printed circuit board in an array configuration where, after reheat, the balls connect the chip to the printed circuit board. BGA""s are known with 40, 50 and 60 mil spacings in regular and staggered array patterns.
The packaging arrangements that are typically used for the packaging of semiconductor devices employ a number of different approaches whereby these approaches can be distinguished between methods of providing a (rigid or flexible) support structure on which the semiconductor device is mounted with interconnect lines provided on the surface of the support structure, methods of providing a chip-on-surface mounting technique whereby the supporting structure can contain laminated layers of interconnect lines that are used in combination with interconnect lines on the surface of the supporting structure and methods of providing laminated packages that use cavities for the mounting of the semiconductor devices. Where possible, the methods of packaging are designed such that automated packaging processes can be used for obvious reasons of costs incurred as part of the packaging process. In this respect, the supporting structure that uses a cavity for the mounting of the semiconductor device does not lend itself to automatic packaging processes since, for the various packaging approaches that have been highlighted, the semiconductor device must, after it has been packaged, as yet be encapsulated, which is a processing step that cannot readily be monitored using cavity based supporting structures.
For the typical mounting of a chip on the surface of a laminated substrate, whereby the substrate can be either ceramic (making the substrate rigid) or can contain an organic or plastic material (making the substrate flexible), electrical interconnect lines are formed in the laminated layers of the substrate using conventional methods of metal deposition and patterning that apply standard photolithographic methods and procedures. The various layer of the laminated substrate are insulated from each other using dielectric materials such as a polyimide that can be used to separate for instance metal power and ground planes in the substrate. Electrical connections between the layers of the laminated substrate are formed by conductive vias, the opening of the via is, after this opening has been formed, filled with a conductive material in order to establish the electrically conductive paths between the various layers. After the required interconnect patterns have in this manner been established in the laminated substrate, the semiconductor chip is positioned on the surface of the substrate and attached to the substrate by a suitable die attach material such as epoxy. This layer of epoxy serves not only to hold the semiconductor die in place but also serves as a heat transfer medium between the die and the substrate. The top surface of the semiconductor die is connected (wire bonded) to the conductive traces on the surface of the substrate, after which the die including the bonded wires can be encapsulated. Electrical interconnects must then be established between the substrate (to which the die is at this time connected) and the surrounding electrical circuits to which the substrate is connected. Electrical traces are also provided in the lower surface of the substrate, a solder mask is deposited over the bottom surface of the substrate, contact balls are positioned in alignment with the contact points in the lower surface of the substrate and re-flowed, connecting the contact balls with the electrical traces in the bottom surface of the substrate and completing the interconnects between the (surface mounted) semiconductor die and the contact balls of the supporting substrate. The method described above is a method of connecting a semiconductor device using wire bond techniques. In addition and as a substitute to the wire bond techniques, known connection techniques in the art such as flip-chip techniques can be applied to interconnect the semiconductor die.
Another important consideration in designing semiconductor packages is the aspect of heat dissipation, an aspect that becomes even more important for devices that operate at high operating speeds or at high levels of voltage. For the purpose of heat dissipation, a semiconductor device can be mounted on a heat sink whereby the heat dissipation can be enhanced by providing a low thermal resistivity path between the semiconductor device and the heat sink. Methods that are applied to conduct heat from the die to the heat sink and from the heat sink to the environment for further dissipation are well know in the art.
For all of the above indicated aspects of semiconductor device packaging and for other aspects that may not have been enumerated above, it is important that in a high speed, high throughput manufacturing environment semiconductor devices can be readily identified with respect to die surface and how, as a consequence, the device must be mounted in for instance a heat sink. Lack of fast and correct identification leads to misplaced and incorrectly placed devices, resulting in increased production costs. A method must therefore be provided that assures fast and correct identification of device surfaces, the method of the invention addresses this problem of device identification.
U.S. Pat. No. 5,895,967 (Stearns et al.) shows a BGA with a stiffener and spreader.
U.S. Pat. No. 5,977,626 (Wang et al.) teaches a heat spreader for a PBGA.
U.S. Pat. No. 5,768,774 (Wilson et al.) shows a BGA package with a heat sink. However, this reference differs from the invention.
U.S. Pat. No. 6,011,304 (Mertol) shows a stiffer ring attachment p3 le and removable snap in heat spreader lid.
A principle objective of the invention is to provide a method that allows for easy and dependable identification of semiconductor device orientation.
Another objective of the invention is to prevent errors that are introduced due to incorrect device surface or orientation identification.
Yet another objective of the invention is to provide a method that simplifies the verification of semiconductor devices in a high speed, high throughput semiconductor manufacturing environment.
A still further objective of the invention is to provide a method of semiconductor device identification that has no negative effect on device throughput.
A still further objective of the invention is to provide a method of device identification that applies to both small and large devices and that is independent of the device I/O count.
In accordance with the objectives of the invention a new method is provided to identify semiconductor devices. Prior Art methods of device identification use a cutout on one side of the device or a chamfer (removed corner) of the device for this purpose. This method run into problems where packages with high I/O pin count are required since the space that is required for the chamfer may interfere with or limit the number of I/O pins that can be provided on the bottom of the package. For this reason, the invention provides for a shallow depression or hole on the backside of the heat sink of the package. This shallow depression can be used for visual and optical inspection of the device orientation.